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Rev 0; 11/03
3.3V Spread-Spectrum EconOscillator
General Description
The DS1086L EconOscillatorTM is a 3.3V programmable clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 130kHz to 66.6MHz. The selectable dithered output reduces radiated-emission peaks by dithering the frequency 0.5%,1%, 2%, 4%, or 8% below the programmed frequency. The DS1086L has a power-down mode and an output-enable control for power-sensitive applications. All the device settings are stored in nonvolatile (NV) EEPROM memory allowing it to operate in stand-alone applications.
Features
User-Programmable Square-Wave Generator Frequencies Programmable from 130kHz to 66.6MHz 0.5%, 1%, 2%, 4%, or 8% Selectable Dithered Output Adjustable Dither Rate Glitchless Output-Enable Control 2-Wire Serial Interface Nonvolatile Settings 2.7V to 3.6V Supply No External Timing Components Required Power-Down Mode 5kHz Master Frequency Step Size EMI Reduction Industrial Temperature Range: -40C to +85C
DS1086L
Applications
Printers Copiers PCs Computer Peripherals Cell Phones Cable Modems
Ordering Information
PART DS1086LU TEMP RANGE -40C to +85C PIN-PACKAGE 8 SOP (118 mil)
Typical Operating Circuit
DITHERED 130kHz TO 66.6MHz OUTPUT VCC N.C. OUT SPRD VCC GND DECOUPLING CAPACITORS (0.1F and 0.01F) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. SCL* VCC
Pin Configuration
TOP VIEW
P XTL1/OSC1 XTL2/OSC2
OUT 1 SPRD 2
8 7
SCL SDA PDN OE
DS1086L
SDA* PDN OE
DS1086L
VCC 3 6 5 GND 4
SOP
EconOscillator is a trademark of Dallas Semiconductor.
______________________________________________ Maxim Integrated Products
1
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3.3V Spread-Spectrum EconOscillator DS1086L
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to Ground ..........-0.5V to +6.0V Voltage Range on SPRD, PDN, OE, SDA, and SCL Relative to Ground* ..................................-0.5 to (VCC + 0.5V) *This voltage must not exceed 6.0V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range ...........................-40C to +85C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature ..................See IPC/JEDEC J-STD-020A
RECOMMENDED DC OPERATING CONDITIONS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER Supply Voltage High-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) Low-Level Input Voltage (SDA, SCL SPRD, PDN, OE) SYMBOL VCC VIH VIL (Note 1) CONDITIONS MIN 2.7 0.7 x VCC -0.3 TYP 3.3 MAX 3.6 VCC + 0.3 0.3 x VCC UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER High-Level Output Voltage (OUT) Low-Level Output Voltage (OUT) Low-Level Output Voltage (SDA) High-Level Input Current Low-Level Input Current Supply Current (Active) Standby Current (Power-Down) SYMBOL VOH VOL VOL1 VOL2 IIH IIL ICC ICCQ IOL = 4mA 3mA sink current 6mA sink current VCC = 3.6V VIL = 0 CL = 15pF (output at default frequency) Power-down mode -1 10 10 CONDITIONS IOH = -4mA, VCC = min MIN 2.4 0 0 0 0.4 0.4 0.6 1 TYP MAX UNITS V V V A A mA A
2
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3.3V Spread-Spectrum EconOscillator
MASTER OSCILLATOR CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER Master Oscillator Frequency Default Master Oscillator Frequency Master Oscillator Frequency Tolerance Voltage Frequency Variation SYMBOL fOSC f0 f0 f0 fV f0 fT f0 (Note 2) Factory-programmed default VCC = 3.3V, TA = +25C (Notes 3,17) Over voltage range, TA = +25C (Note 4) Over temperature range, VCC = 3.3V (Note 5) Default frequency (f0) DAC step size Default frequency DAC step size Default frequency 66.6MHz 33.3MHz -0.5 -0.5 -0.75 -0.75 -2.0 -2.0 -2.5 0.5 1 2 4 8 -0.6 5 5.12 500 2.56 RANGE (5 LSBs of RANGE register) f0/8192 f0/4096 f0/2048 Hz +0.3 % kHz MHz decimal MHz % CONDITIONS MIN 33.3 48.65 +0.5 % +0.5 +0.75 +0.75 +0.75 +0.75 +0.75 % % TYP MAX 66.6 UNITS MHz MHz
DS1086L
Temperature Frequency Variation
Prescaler bits JS2, JS1, JS0 = 000 Dither Frequency Range (Note 6) f f0 Prescaler bits JS2, JS1, JS0 = 001 Prescaler bits JS2, JS1, JS0 = 010 Prescaler bits JS2, JS1, JS0 = 100 Prescaler bits JS2, JS1, JS0 = 111 Integral Nonlinearity of Frequency DAC Step Size DAC Span DAC Default Offset Step Size INL Entire range (Note 7) between two consecutive DAC values (Note 8) Frequency range for one offset setting (Table 2) Factory default register setting between two consecutive offset values (Table 2) OS Factory default OFFSET register setting (5 LSBs) (Table 2) Prescaler bits JS4, JS3 = 00 Dither Rate Prescaler bits JS4, JS3 = 01 Prescaler bits JS4, JS3 = 10
Offset Default
hex
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3.3V Spread-Spectrum EconOscillator DS1086L
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER Frequency Stable After Prescaler Change Frequency Stable After DAC or Offset Change Power-Up Time Enable of OUT After Exiting Power-Down Mode OUT High-Z After Entering Power-Down Mode Load Capacitance Output Duty Cycle (OUT) Rise and Fall Time (OE, PDN) tDACstab (Note 9) 0.1 0.1 SYMBOL CONDITIONS MIN TYP MAX 1 1 0.5 200 100 (Note 11) Default frequency 45 15 50 55 1 UNITS period ms ms s s pF % s
tpor + tstab (Note 10) tstab tpdn CL (Note 18)
AC ELECTRICAL CHARACTERISTICS--2-WIRE INTERFACE
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition LOW Period of SCL HIGH Period of SCL Setup Time for a Repeated START Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF CONDITIONS Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 12) (Note 12) (Notes 12, 13) (Note 12) (Note 12) (Note 12) (Notes 12, 14, 15) (Note 12) (Note 16) (Note 16) 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 100 250 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.9 MIN TYP MAX 400 100 UNITS kHz s s s s s s ns 300 1000 300 1000 ns ns
4
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3.3V Spread-Spectrum EconOscillator
AC ELECTRICAL CHARACTERISTICS--2-WIRE INTERFACE (continued)
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER Setup Time for STOP Capacitive Load for Each Bus Line EEPROM Write Cycle Time Input Capacitance SYMBOL tSU:STO CB tWR CI 5 Fast mode Standard mode (Note 16) CONDITIONS MIN 0.6 4.0 400 10 TYP MAX UNITS s pF ms pF
DS1086L
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = 2.7V to 3.6V)
PARAMETER EEPROM Writes SYMBOL +70C CONDITIONS MIN 10,000 TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5:
Note 6: Note 7: Note 8: Note 9: Note 10:
Note 11: Note 12:
Note 13: Note 14: Note 15: Note 16: Note 17:
Note 18:
All voltages are referenced to ground. DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range. Correct operation of the device is not guaranteed if these limits are exceeded. This is the absolute accuracy of the master oscillator frequency at the default settings. This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at TA = +25C. This is the percentage frequency change from the +25C frequency due to temperature at VCC = 3.3V. The maximum temperature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequency (fdefault). The maximum occurs at the extremes of the master oscillator frequency range (33.3MHz or 66.6MHz). The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. The integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two endpoints (fosc(MIN) to fosc(MAX)) of the range. The error is in percentage of the span. This is true when the prescaler = 1. Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original value to the new value. This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and therefore depends on the programmed clock frequency. Output voltage swings can be impaired at high frequencies combined with high output loading. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. CB--total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Typical frequency shift due to aging is 0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr +125C bake, 168hr 85C/85%RH moisture soak, and three solder reflow passes +240 +0/-5C peak) followed by 1000hr max VCC biased 125C HTOL, 1000 temperature cycles at -55C to +125C, 96hr 130C/85%RH/3.6V HAST and 168hr 121C/2 ATM Steam/Unbiased Autoclave. tstab is the time required after exiting power-down to the beginning of output oscillations. In addition, a delay of tDACstab is required before the frequency will be within its specified tolerance.
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3.3V Spread-Spectrum EconOscillator DS1086L
Typical Operating Characteristics
(VCC = 3.3V, TA = 25C, unless otherwise noted.)
SUPPLY CURRENT vs. MASTER OSCILLATOR FREQUENCY
8 SUPPLY CURRENT (mA) 7 6 5 4 3 2 PRESCALER = 1 1 33 36 39 42 45 48 51 54 57 60 63 66 MASTER FREQUENCY (MHz) 3 -40 -15 10 35 60 85 TEMPERATURE (C) 4.7pF LOAD 15pF LOAD
DS1086L toc01
SUPPLY CURRENT vs. TEMPERATURE
DS1086L toc02
SUPPLY CURRENT vs. PRESCALER
DS1086L toc03
9
10 9 SUPPLY CURRENT (mA) 8 7 6 5 4 fO = 33.3MHz PRESCALER = 1 15pF LOAD fO = 50MHz fO = 66MHz
7 6 SUPPLY CURRENT (mA) 5 4 3 2 1 0 1 10 PRESCALER 100 fO = 50MHz 15pF LOAD
1000
MASTER OSCILLATOR FREQUENCY PERCENT CHANGE vs. SUPPLY VOLTAGE
DS1086L toc04
MASTER OSCILLATOR FREQUENCY PERCENT CHANGE vs. TEMPERATURE
DS1086L toc05
DUTY CYCLE vs. TEMPERATURE
DS1086L toc06
0.5 0.4 0.3 PERCENT CHANGET (%) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.7 3.0 3.3 PRESCALER = 1 fO = 50MHz fO = 33.3MHz fO = 66MHz
0.50 0.25 PERCENT CHANGE (%) 0 fO = 33.3MHz
55
54 DUTY CYCLE (%) fO = 66MHz
-0.25 -0.50 -0.75 -1.00 -1.25 -1.50 PRESCALER = 1 15pF LOAD -40 -15 10 35 60 85 fO = 50MHz fO = 66MHz
53
52 fO = 50MHz 51 fO = 33.3MHz PRESCALER = 1 50 -40 -15 10 35 60 85
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
TEMPERATURE (C)
DUTY CYCLE vs. SUPPLY VOLTAGE
DS1086L toc07
55
54 DUTY CYCLE (%)
fO = 66MHz
53
52
fO = 50MHz fO = 33.3MHz PRESCALER = 1 2.7 3.0 3.3 3.6
51
SUPPLY VOLTAGE (V)
6
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3.3V Spread-Spectrum EconOscillator
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = 25C, unless otherwise noted.)
DS1086L
POWER-DOWN CURRENT vs. SUPPLY VOLTAGE
DS1086L toc08
POWER-DOWN CURRENT vs. TEMPERATURE
1.62 POWER-DOWN CURRENT (A) 1.60 1.58 1.56 1.54 1.52 1.50 1.48 1.46 1.44 -40 -15 10 35 60 85
DS1086L toc09
1.8 1.7 POWER-DOWN CURRENT (A) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.7 3.0 3.3
1.64
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT WITH OUTPUT DISABLED vs. SUPPLY VOLTAGE
DS1086L toc10
SUPPLY CURRENT WITH OUTPUT DISABLED vs. TEMPERATURE
DS1086L toc11
4.0 3.5 SUPPLY CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0 2.7 3.0 fO = 66MHz
2.7
2.6 SUPPLY CURRENT (mA)
2.5
2.4
2.3 fO = 66MHz 2.2 3.3 3.6 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
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3.3V Spread-Spectrum EconOscillator DS1086L
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME OUT SPRD VCC GND OE PDN SDA SCL FUNCTION Oscillator Output. The output frequency is determined by the OFFSET, DAC, and prescaler registers. Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled. Power Supply Ground Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled but the master oscillator is still on. Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator is disabled (power-down mode). 2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain and can be wire-ORed with other open-drain or open-collector interfaces. 2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out on falling edges.
SPECTRUM COMPARISON (12OkHz BW, SAMPLE DETECT)
-10 POWER SPECTRUM (dBm) -20 -30 -40 -50 -60 -70 -80 -90 43 45 47 49 51 53 FREQUENCY (MHz) fo = 50MHz DITHER RATE = fo/4096 8% 2% 0.5% NO SPREAD
DS1086L fig01
MAXIMUM THERMAL VARIATION vs. MASTER OSCILLATOR FREQUENCY
2% SUPPLY CURRENT (mA) 1% 0 -1% -2% -3% -4% -5% 33 36 39 42 45 48 51 54 57 60 63 66 MASTER FREQUENCY (MHz)
DS1086L fig02
0
3%
Figure 1. Clock Spectrum Dither Comparison
Figure 2. Temperature Variation Over Frequency
Processor-Controlled Mode
VCC P XTL1/OSC1 DITHERED 260kHz TO 133MHz OUTPUT VCC OUT SPRD VCC GND DECOUPLING CAPACITORS (0.1F and 0.01F) 4.7k SCL SDA 4.7k XTL2/OSC2 N.C.
Stand-Alone Mode
DITHERED 130kHz TO 66.6MHz OUTPUT VCC OUT SPRD VCC SCL* VCC
DS1086L
SDA* PDN OE
DS1086
PDN OE
VCC
2-WIRE INTERFACE
GND DECOUPLING CAPACITORS (0.1F and 0.01F)
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
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3.3V Spread-Spectrum EconOscillator DS1086L
VCC VCC SDA SCL 2-WIRE INTERFACE EEPROM CONTROL REGISTERS DAC OFFSET ADDR RANGE PRESCALER FREQUENCY CONTROL VOLTAGE DAC
DS1086L
PDN
VOLTAGE-CONTROLLED OSCILLATOR MASTER OSCILLATOR OUTPUT PRESCALER BY 1, 2, 4...256 OUT
DITHER CONTROL
OE SPRD GND TRIANGLE WAVE GENERATOR
DITHER SIGNAL
Figure 3. Block Diagram
Detailed Description
A block diagram of the DS1086L is shown in Figure 3. The internal master oscillator generates a square wave with a 33.3MHz to 66.6MHz frequency range. The frequency of the master oscillator can be programmed with the DAC register over a two-to-one range in 5kHz steps. The master oscillator range is larger than the range possible with the DAC step size, so the OFFSET register is used to select a smaller range of frequencies over which the DAC spans. The prescaler can then be set to divide the master oscillator frequency by 2 x (where x equals 0 to 8) before routing the signal to the output (OUT) pin. A programmable triangle-wave generator injects an offset element into the master oscillator to dither its output 0.5%, 1%, 2%, 4%, or 8%. The dither magnitude is controlled by the JS2, JS1, and JS0 bits in the PRESCALER word and enabled with the SPRD pin. Futhermore, the dither rate is controlled by the JS4 and JS3 bits in the PRESCALER word and determines the frequency of the dither. The maximum spectral attenuation occurs when the prescaler is set to 1 and is reduced by 2.7dB for every factor of 2 that is used in the prescaler. This hap-
pens because the prescaler's divider function tends to average the dither in creating the lower frequency. However, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. The external control input, OE, gates the clock output buffer. The PDN pin disables the master oscillator and turns off the clock output for power-sensitive applications*. On power-up, the clock output is disabled until power is stable and the master oscillator has generated 512 clock cycles. Both controls feature a synchronous enable that ensures there are no output glitches when the output is enabled. The control registers are programmed through a 2-wire interface and are used to determine the output frequency and settings. Once programmed into EEPROM, since the register settings are NV, the settings only need to be reprogrammed if it is desired to reconfigure the device.
*The power-down command must persist for at least two output frequency cycles plus 10s for deglitching purposes. 9
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3.3V Spread-Spectrum EconOscillator DS1086L
Table 1. Register Summary
REGISTER PRESCALER PRESCALER DAC (MSB) DAC (LSB) OFFSET ADDR RANGE WRITE EE ADDR 02h -- 08h -- 0Eh 0Dh 37h 3Fh MSB JS4 P1 b9 b1 X1 X1 XX JS3 P0 b8 b0 X1 X1 XX JS2 XX b7 X0 X1 X1 XX BINARY JS1 JS0 XX XX b6 b5 X0 X0 b4 b3 X1 WC b4 b3 NO DATA LO/HiZ XX b4 X0 b2 A2 b2 P3 XX b3 X0 b1 A1 b1 LSB P2 XX b2 X0 b0 A0 b0 FACTORY DEFAULT 0110000 0 00XXXXX 01111101b 00000000b 111- ----b 11110000b xxx- - - - - b
--
ACCESS R/W R/W R/W R/W R/W R/W R
--
X0 = Don't care, reads as zero. X1 = Don't care, reads as one. XX = Don't care, reads indeterminate. X = Don't care.
Table 2. Offset Settings
OFFSET OS - 6 OS - 5 OS - 4 OS - 3 OS - 2 OS - 1 OS* OS + 1 OS + 2 OS + 3 OS + 4 OS + 5 OS + 6 FREQUENCY RANGE (MHz) 30.7 to 35.8 33.3 to 38.4 35.8 to 41.0 38.4 to 43.5 41.0 to 46.1 43.5 to 48.6 46.1 to 51.2 48.6 to 53.8 51.2 to 56.3 53.8 to 58.9 56.3 to 61.4 58.9 to 64.0 61.4 to 66.6
See the Example Frequency Calculations section for a more in-depth look at using the registers.
________________Register Definitions
The DS1086L registers are used to program the output frequency, dither percent, dither rate, and 2-wire address. Table 1 shows a summary of the registers and detailed descriptions follow below.
PRESCALER (02h)
The PRESCALER word is a two-byte value containing control bits for the prescaler (P3 to P0), output control (Lo/HiZ), the jitter rate (JS4 to JS3), as well as control bits for the jitter percentage (JS2 to JS0). The PRESCALER word is read and written using two-byte reads and writes beginning at address 02h. JS4 to JS3: Jitter Rate. This is the frequency of the triangle wave generator and the modulation frequency that the output is dithered. It can be programmed to the master oscillator frequency, fOSC, divided by either 8192, 4096, or 2048.
JS4 0 0 1 JS3 0 1 0 JITTER RATE fOSC/8192 fOSC/4096 (default) fOSC/2048
*Factory default setting. OS is the integer value of the five LSBs of the RANGE register.
The output frequency is determined by the following equation:
fOUTPUT =
(MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE x 5 kHz STEP SIZE) PRESCALER
where: min frequency of selected OFFSET range is the lowest frequency (shown in Table 2 for the corresponding offset). DAC value is the value of the DAC register (0 to 1023). Prescaler is the value of 2x where x = 0 to 8.
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3.3V Spread-Spectrum EconOscillator
JS2 to JS0: Jitter Percentage. These three bits select the amount of jitter in percent. The SPRD pin must be a logic high for the jitter to be enabled. Bit combinations not shown are reserved.
JS2 0 0 0 1 1 JS1 0 0 1 0 1 JS0 0 1 0 0 1 JITTER % 0.5 1 2 4 8
required to program new master oscillator frequencies shown in Table 2. The read-only backup is important because the offset register is EEPROM and is likely to be overwritten.
DS1086L
ADDR (0Dh)
WC: EEPROM Write Control Bit. The WC bit enables/disables the automatic writing of registers to EEPROM. This prevents EEPROM wear out and eliminates the EEPROM write cycle time. If WC = 0 (default), register writes are automatically written to EEPROM. If WC = 1, register writes are stored in SRAM and only written into EEPROM when the user sends a WRITE EE command. If power is cycled to the device, then the last value stored in EEPROM is recalled. WC = 1 is ideal for applications that frequently modify the frequency/registers. Regardless of the value of the WC bit, the value of the ADDR register is always written immediately to EEPROM. A2 to A0: Device Address Bits. These bits determine the 2-wire slave address of the device. They allow up to eight devices to be attached to the same 2-wire bus and to be addressed individually.
Lo/HiZ: Output Low or High-Z. This bit determines the state of the output pin when the device is in powerdown mode or when the output is disabled. If Lo/HiZ = 0, the output is HiZ when in power-down or disabled. If Lo/HiZ = 1, the output is held low when in power-down or disabled. P3 to P0: Prescaler Divider. These bits divide the master oscillator frequency by 2x, where x is P3 to P0 and can be from 0 to 8. Any prescaler value entered greater than 8 decodes as 8.
DAC (08h)
B9 to B0: DAC Setting. The DAC word sets the master oscillator frequency to a specific value within the current offset range. Each step of the DAC changes the master oscillator frequency by 5kHz. The DAC word is read and written using two-byte reads and writes beginning at address 08h.
WRITE EE Command (3Fh)
This command can be used when WC = 1 (see the WC bit in ADDR register) to transfer all registers from SRAM into EEPROM. The time required to store the values is one EEPROM write cycle time. This command is not needed if WC = 0.
OFFSET (0Eh)
B4 to B0: Offset. This value selects the master oscillator frequency range that can be generated by varying the DAC word. Valid frequency ranges are shown in Table 2. Correct operation of the device is not guaranteed for values of OFFSET not shown in the table. The default offset value (OS) is factory trimmed and can vary from device to device. Therefore, to change frequency range, OS must be read so the new offset value can be calculated relative to the default. For example, to generate a master oscillator frequency within the largest range (61.4MHz to 66.6MHz), Table 2 indicates that the OFFSET must be programmed to OS + 6. This is done by reading the RANGE register and adding 6 to the value of bits B4 to B0. The result is then written into bits B4 to B0 of the OFFSET register. Additional examples are provided in the Example Frequency Calculations section.
RANGE (37h)
B4 to B0: Range: This read-only, factory programmed value is a copy of the factory default offset (OS). OS is
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3.3V Spread-Spectrum EconOscillator DS1086L
Example Frequency Calculations
Example #1: Calculate the register values needed to generate a desired output frequency of 11.0592MHz. Since the desired frequency is not within the valid master oscillator range of 33.3MHz to 66.6MHz, the prescaler must be used. Valid prescaler values are 2x where x equals 0 to 8 (and x is the value that is programmed into the P3 to P0 bits of the PRESCALER register). Equation 1 shows the relationship between the desired frequency, the master oscillator frequency, and the prescaler.
f fDESIRED = MASTER OSCILLATOR prescaler fMASTER OSCILLATOR 2X =
Valid values of DAC are 0 to 1023 (decimal) and 5kHz is the step size. Equation 4 is derived from rearranging Equation 3 and solving for the DAC value.
DAC VALUE =
(fMASTER OSCILLATOR - MIN FREQUENCY OF SELECTED OFFSET RANGE) 5kHz STEP SIZE
(4)
DAC VALUE =
(1)
(44.2368MHz - 41.0MHz) 5kHz STEP SIZE = 647.36 647 (decimal)
By trial and error, x is incremented from 0 to 8 in Equation 2, finding values of x that yield master oscillator frequencies within the range of 33.3MHz to 66.6MHz. Equation 2 shows that a prescaler of 4 (x = 2) and a master oscillator frequency of 44.2368MHz generates our desired frequency. Writing 0080h to the PRESCALER register sets the PRESCALER to 4. Be aware that other settings also reside in the PRESCALER register.
fMASTER OSCILLATOR = fDESIRED x prescaler = fDESIRED x 2X fMASTER OSCILLATOR = 11.0592MHz x 22 = 44.2368MHz
Since the two-byte DAC register is left justified, 647 is converted to hex (0287h) and bit-wise shifted left six places. The value to be programmed into the DAC register is A1C0h. In summary, the DS1086L is programmed as follows: PRESCALER = 0080h OFFSET = OS - 2 or 10h (if range was read as 12h) DAC = A1C0h Notice that the DAC value was rounded. Unfortunately, this means that some error is introduced. To calculate how much error, a combination of Equation 1 and Equation 3 is used to calculate the expected output frequency. See Equation 5.
(2)
Once the target master oscillator frequency has been calculated, the value of offset can be determined. Using Table 2, 44.2368MHz falls within both OS - 1 and OS - 2. However, choosing OS - 1 would be a poor choice since 44.2368MHz is so close to OS - 1's minimum frequency. On the other hand, OS - 2 is ideal since 44.2368MHz is close to the center of OS - 2's frequency span. Before the OFFSET register can be programmed, the default value of offset (OS) must be read from the RANGE register (last five bits). In this example, 12h (18 decimal) was read from the RANGE register. OS - 2 for this case is 10h (16 decimal). This is the value that is written to the OFFSET register. Finally, the two-byte DAC value needs to be determined. Since OS - 2 only sets the range of frequencies, the DAC selects one frequency within that range as shown in Equation 3.
fMASTER OSCILLATOR = (MIN FREQUENCY OF SELECTED OFFSET
RANGE) + (DAC value x 5kHz)
(MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE x 5kHz STEP SIZE) fOUTPUT = prescaler (41.0MHz) + (647 x 5kHz) fOUTPUT = = 4 44.235MHz = 11.05875MHz 4
(5)
(3)
12
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3.3V Spread-Spectrum EconOscillator DS1086L
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 4. 2-Wire Data Transfer Protocol
The expected output frequency is not exactly equal to the desired frequency of 11.0592MHz. The difference is 450Hz. In terms of percentage, Equation 6 shows that the expected error is 0.004%. The expected error assumes typical values and does not include deviations from the typical as specified in the electrical tables.
fDESIRED - fEXPECTED x 100 fDESIRED
Finally, the DAC value is calculated as shown in Equation 8. (8)
DAC VALUE = (50.0MHz - 48.6MHz) = 280.00 (decimal) 5kHz STEP SIZE
%ERROREXPECTED =
(6)
%ERROREXPECTED =
11.0592MHz - 11.05875MHz x 100 11.0592MHz 450Hz = x 100 = 0.004% 11.0592MHz
The result is then converted to hex (0118h) and then left-shifted, resulting in 4600h to be programmed into the DAC register. In summary, the DS1086L is programmed as follows: PRESCALER = 0000h OFFSET = OS + 1 or 13h (if RANGE was read as 12h) DAC = 4600h
Example #2: Calculate the register values needed to generate a desired output frequency of 50MHz. Since the desired frequency is already within the valid master oscillator frequency range, the prescaler is set to divide by 1, and hence, PRESCALER = 0000h (currently ignoring the other setting). (7)
fMASTER OSCILLATOR = 50.0MHz x 20 = 50.0MHz
fOUTPUT
=
(48.6MHz) + (280 x 5kHz)
= 20 50.0MHz = 50.0MHz 1
(9)
Since the expected output frequency is equal to the desired frequency, the calculated error is 0%.
Next, looking at Table 2, OS + 1 provides a range of frequencies centered around the desired frequency. To determine what value to write to the OFFSET register, the RANGE register must first be read. Assuming 12h was read in this example, 13h (OS + 1) is written to the OFFSET register.
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13
3.3V Spread-Spectrum EconOscillator DS1086L
MSB 1 0 1 1 A2 A1 A0
LSB R/W
Figure 5. Slave Address
SDA
tBUF tLOW tR tF
REA
D/W
RIT EB
DEVICE IDENTIFIER
DEVICE ADDRESS
IT
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 6. 2-Wire AC Characteristics
_______2-Wire Serial Port Operation
2-Wire Serial Data Bus
The DS1086L communicates through a 2-wire serial interface. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a "master." The devices that are controlled by the master are "slaves." A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1086L operates as a slave on the 2wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see Figures 4 and 6): * Data transfer can be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP con-
14
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3.3V Spread-Spectrum EconOscillator
ditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1086L works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. When the DS1086L EEPROM is being written to, it is not able to perform additional responses. In this case, the slave DS1086L sends a not acknowledge to any data transfer request made by the master. It resumes normal operation when the EEPROM operation is complete. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figures 4, 5, 6, and 7 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1086L can operate in the following two modes: Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1086L while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
DS1086L
Slave Address
Figure 5 shows the first byte sent to the device. It includes the device identifier, device address, and the R/W bit. The device address is determined by the ADDR register.
Registers/Commands
See Table 1 for the complete list of registers/commands and Figure 7 for an example of using them.
__________Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1086L, decouple the power supply with 0.01F and 0.1F high-quality, ceramic, surface-mount capacitors. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. These capacitors should be placed as close to pins 3 and 4 as possible.
Stand-Alone Mode
SCL and SDA cannot be left floating when they are not used. If the DS1086L never needs to be programmed in-circuit, including during production testing, SDA and SCL can be tied high. The SPRD pin must be tied either high or low.
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15
3.3V Spread-Spectrum EconOscillator DS1086L
TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 0 1 1 LSB A2* A1* A0* R/W DEVICE ADDRESS READ/ WRITE SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
DEVICE IDENTIFIER
COMMAND/REGISTER ADDRESS
DATA
EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) B0h 0Eh SLAVE SLAVE A) SINGLE BYTE WRITE START 1 0 1 1 0 0 0 0 ACK 0 0 0 0 1 1 1 0 ACK -WRITE OFFSET REGISTER B0h B) SINGLE BYTE READ -READ OFFSET REGISTER START 1 0 1 1 0 0 0 0 0Eh SLAVE SLAVE 00001110 ACK ACK
DATA OFFSET SLAVE ACK B1h REPEATED START DATA DAC MSB SLAVE ACK B1h REPEATED START 10110001 SLAVE ACK 10110001 SLAVE ACK DATA DAC LSB SLAVE ACK DATA DAC MSB MASTER ACK STOP STOP
DATA OFFSET MASTER NACK STOP
C) TWO BYTE WRITE -WRITE DAC REGISTER
B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK
DATA DAC LSB MASTER NACK STOP
D) TWO BYTE READ -READ DAC REGISTER
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET IN THE ADDR REGISTER.
Figure 7. 2-Wire Transactions
Chip Topology
TRANSISTOR COUNT: 9052 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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